Parallel serial converter verilog

I took a look at the kinds of thing that are available in the 74 series of logic chips and came up with the 4-bit right-shift register.

It actually offers a bit more than we need since it can shift in both directions and we only need to go to the right. It adds not only a parallel input but also two control inputs and an asynchrnous reset input. It is designed to cascade trivially so I am quite happy to produce the Verilog version of an 8-bit universal register register with four modes.

Here is my first try. Note that I have used a 2-bit mode input instead of separate S1 and S0 inputs. All went well until I set mode to 1. Find centralized, trusted content and collaborate around the technologies you use most. Connect and share knowledge within a single location that is structured and easy to search. I am looking to design a serial to parallel converter in Verilog which converts a fast clock serial input to a slower clock parallel input.

The serial data comes in at nclk and the parallel data is intended to come out at clk rate. Following is the code that I have come up with which works well in functional simulation but Formal Verification fails. I feel you should use four bits in order to index 16 elements. If you parameterize the module, this could be done with:.

Also, you might want to include a clock synchronizer, you don't want metastability problems, an easy way to do this is to include "double-triggers", practically is to buffer the data and replicate it to the next slow clock cycle adds 1 slow clock cycle latency.

So, maybe this works:. Stack Overflow for Teams — Collaborate and share knowledge with a private group. Create a free Team What is Teams? Collectives on Stack Overflow. Learn more. Ask Question. Asked 1 year, 5 months ago. Active 1 year, 5 months ago. Viewed 1k times.